The present invention relates to a semiconductor apparatus (including a microcomputer) with a memory and logic circuit integrated into a single chip.
A conventional dynamic RAM 1000 is constructed as shown in FIG. 16 and operates according to a timing chart shown in FIG. 17. More specifically, time t0 to t3 indicates a read cycle and time t3 to t6 indicates a write cycle.
First, the operation of the read cycle of time t0 to t3 will be explained. In the following explanations, a signal that becomes active at an xe2x80x9cLxe2x80x9d level or an inverted signal is expressed with xe2x80x9c/xe2x80x9d prefixed to the signal name.
Since a /row enable signal (row enable signal that becomes active at an xe2x80x9cLxe2x80x9d level) is xe2x80x9cLxe2x80x9d on the rising edge of a time t0 clock signal, a row address R0 is latched and output by a D type flip flop (hereinafter referred to as xe2x80x9cDFFxe2x80x9d) of a row address latch circuit 1002. A row decoder 1004 starts decoding at a point in time when R0 is output as the latch data of the above described row address, reads data of a memory cell connected to a word line (hereinafter referred to as xe2x80x9cWLxe2x80x9d) selected by the decoding result to a bit line or /bit line and amplifies the data using 1024 sense amplifiers.
At time t1, a /row selection control signal is xe2x80x9cLxe2x80x9d and a /column selection control signal is xe2x80x9cLxe2x80x9d, and therefore a /column enable signal is driven xe2x80x9cLxe2x80x9d and a column address C0 is latched and output by a DFF of a column address latch circuit 1001 on the rising edge of the clock signal.
Decoding starts at a point in time when C0 is output as the latch data of the above described column address, one of four column selection signals (3:0) is enabled, 256 bit lines and /bit lines are selected from among the bit lines and /bit lines amplified by the above described 1024 sense amplifiers, amplified by a main amplifier and output to data outputs (255:0). Next, the operation of the write cycle of time t3 to t6 will be explained.
At time t3, the same operation as that at time t0 is performed, one of WL (255:0) is selected by R1 to carry out the same operation as that at time t0, connected to a bit line and /bit line selected by a column address C1 and data of data inputs (255:0) is written in memory cells whose WL is enabled.
However, in the conventional configuration, row addresses and column addresses are latched by DFF, decoding of an address is started a certain time after the clock for confirming the DFF address has risen, which lengthens the time after the clock rise until WL is selected and the time after the clock rise until column selection signals (3:0) are decoded, and lengthens clock cycles of times t0, t1, t3 and t4 necessary for operation, producing a problem that it is not possible to perform read/write at high speed.
It is an object of the present invention to provide a semiconductor apparatus capable of performing read/write at high speed.
To attain this object, a semiconductor apparatus according to a first aspect of the present invention provides a semiconductor apparatus with a memory and logic section integrated into a single chip, characterized in that the logic section outputs m row addresses from 1st to mth addresses and n column addresses from 1st to. nth addresses to the memory, the memory is constructed of a memory cell array block provided with an input/output section to/from the logic section and a plurality of memory cells, a latch circuit connected to the logic of the input/output section is connected by a scan chain to perform a scan test to test the connection of the logic section, the input/output section is provided with a row address input section and a column address input section, the row address input section is constructed of m latch circuits from 1st to mth row latch circuits, the column address input section is constructed of n latch circuits from 1st to nth column latch circuits, and in the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit, a clock is input to a clock input (CK input), the 1st latch enable signal (1st/latch enable signal) output from the above described memory cell array block is input to an enable signal input (/EN input), the kth row address is input to a data input (D input), an output Q (Q output) is connected to the above described memory cell array block, a shift signal of the above described scan chain data during a scan test is input to a test control signal input (NT input), shift data in a preceding stage of the above described scan chain is input to a test input (DT input), a shift signal to a subsequent stage of the above described scan chain is output to a test output QT (QT output), and in the above described pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit, a clock is input to a clock input (CK input), the 2nd latch enable signal (2nd /latch enable signal) output from the above described memory cell array block is input to an enable signal input (/EN input), the (p-m)th column address is input to a data input (D input), an output Q (Q output) is connected to the above described memory cell array block, a shift signal of the scan chain data during a scan test is input to a test control signal input (NT input), shift data in the preceding stage of the above described scan chain is input to a test input (DT input) and a shift signal to the subsequent stage of the above described scan chain is output to a test output QT (QT output).
The latch circuit according to a second aspect of the present invention is constructed of three inputs; a clock input (CK input), an enable signal input (/EN input) and a data input (D input), and an output Q (Q output), a data input circuit and a data holding circuit, characterized in that the above described data input circuit is fed the above described clock input (CK input), enable signal input (/EN input) and the above described data input (D input) and outputs (DQ3), and when the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described data input (D input) to the above described (DQ3), and when the above described enable signal input (/EN input) is non-active (xe2x80x9cHxe2x80x9d) or when the above described clock input (CK input) is at the 2nd logic level, holds (DQ3) at high impedance, the above described data holding circuit is constructed of an inverter that is fed (A1) and outputs the above described (Q output) and an output control circuit, the above described (A1) is connected to (DQ3), the above described output control circuit has three inputs; the above described output Q (Q output), the above described clock input (CK input) and the above described enable signal input (/EN input), and an output (DO1) input to the above described (A1), and when the above described enable signal input (/EN input) is non-active (xe2x80x9cHxe2x80x9d) or the above described clock input (CK input) is at the 2nd logic level, outputs the inverted level of the above described output Q (Q output) to the above described (DO1), and when the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, holds the above described (DO1) at high impedance.
The latch circuit according to a third aspect of the present invention is a latch circuit provided with a data input circuit and a data holding circuit, characterized in that the above described data input circuit has three Pch transistors connected in series; a Pch transistor whose gate is connected to an enable signal input (/EN input), a Pch transistor whose gate is connected to a data input (D input) and a Pch transistor whose gate is connected to a clock input (CK input), with one end of the above described Pch transistors connected in series connected to a power supply and the other end connected to the input (A1) of the above described data holding circuit, and has three Nch transistors connected in series; an Nch transistor whose gate is connected to (EN) which is an inverted signal of the above described enable signal input (/EN input), an Nch transistor whose gate is connected to a data input (D input) and an Nch transistor whose gate is connected to (/CK) which is an inverted signal of the above described clock input (CK input), with one end of the above described Nch transistors connected in series connected to a reference potential GND and the other end connected to the above described (A1), and the above described data holding circuit is connected to an inverter that is fed the above described (A1) and outputs an output Q (Q output) and a 4th Pch transistor whose gate is connected to an inverted signal (EN) of the above described enable signal input and a 5th Pch transistor whose gate is connected to an inverted signal (/CK) of the above described clock input are connected in parallel, the above described two Pch transistors connected in parallel and a 6th Pch transistor whose gate is connected to the above described output Q are connected in series, with one end of the above described serial connection connected to a power supply and the other end connected to the above described (A1), the 4th Nch transistor whose gate is connected to the above described enable signal input (/EN input) and the 5th Nch transistor whose gate is connected to the above described clock input (CK input) are connected in parallel, the above described two Nch transistors connected in parallel and the 6th Nch transistor whose gate is connected to the above described output Q are connected in series, with one end of the above described serial connection connected to the reference potential GND and the other end connected to the above described (A1).
The latch circuit according to a fourth aspect of the present invention is constructed of five inputs of clock input (CK input), enable signal input (/EN input), test control data input (NT), data input (D input) and test input (DT), and two outputs; an output Q and a test output (QT), 1st latch means, 2nd latch means and 3rd latch means, characterized in that the above described 1st latch means is constructed of a 1st data input circuit and a 1st data holding circuit, the above described 1st data input circuit is fed the above described clock input (CK input), the above described enable signal input (/EN input) and the above described data input (D input) and outputs (DQ1) and when the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described data input (D input) to the above described (DQ1) and when the above described enable signal input (/EN input) is non-active (xe2x80x9cExe2x80x9d) or the above described clock input (CK input) is at the 2nd logic level, holds (DQ1) at high impedance, the above described 1st data holding circuit is constructed of an inverter that is fed (A1) and outputs the above described output Q (Q output) and a 1st output control circuit, the above described (A1) is connected to the above described (DQ3), the above described 1st output control circuit has three inputs; the above described output Q (Q output), the above described clock input (CK input) and the above described enable signal input (/EN input), and an output (DO1) input to the above described (A1) and when the above described enable signal input (/EN input) is nonactive (xe2x80x9cHxe2x80x9d) or the above described clock input (CK input) is at the 2nd logic level, outputs the inverted level of the above described output Q to the above described (DO1) and when the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, holds the above described (DO1) at high impedance, the above described 2nd latch means is constructed of a 2nd data input circuit and a 2nd data holding circuit, has two inputs; a 2nd data input (D2 input) and a 2nd clock input (CK2), and an output (DQ2), and when the above described 2nd clock input (CK2) is at the 1st logic level, outputs the inverted level of the above described 2nd data input (D2 input) to the above described output (DQ2) and when the above described 2nd clock input (CK2) is at the 2nd logic level, holds the above described (DQ2) at high impedance, the above described 2nd data holding circuit is constructed of an inverter that is fed (A2) and outputs above described 2nd output Q2 (Q2), fed the above described (A2) and outputs the above described 2nd output Q2 (Q2) and a 2nd output control circuit, the above described (A2) is connected to the above described (DQ2), the above described 2nd output control circuit has two inputs; the above described 2nd output Q2 (Q2) and the above described 2nd clock input (CK2), and an output (DO2) input to the above described (A2), and when the above described 2nd clock input (CK2) is at the 2nd logic level, outputs the inverted level of the above described 2nd output Q2 (Q2) to the above described (DO2), and when the above described 2nd clock input (CK2) is at the 1st logic level, holds the above described 2nd output Q2 (Q2) at high impedance, the above described 2nd data input (D2 input) is connected to the above described test input (DT) and the above described 2nd clock input (CK2) is connected to the above described clock input (CK input), the above described 3rd latch means is constructed of a 3rd data input circuit and a 3rd data holding circuit, the above described 3rd data input circuit has three inputs; (B3) to which the above described output Q (Q output) is input, (C3) to which the above described 2nd output Q2 (Q2) is input and the above described test control data input (NT) and the above described clock input (CK input), and a 3rd output Q3 (DQ3), and when the above described clock input (CK input) is at the 2nd logic level and the above described test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d), outputs the inverted level of the above described output Q (Q output) to the above described (DQ3), and when the above described test control data input (NT) is active (xe2x80x9cHxe2x80x9d), outputs the inverted level of the above described 2nd output Q2 (Q2) to the above described (DQ3), and when the above described clock input (CK input) is at the 1st logic level, holds the above described (DQ3) at high impedance, the above described 3rd data holding circuit is fed (A3) and outputs a 3rd output Q3 (Q3) and is constructed of an inverter that is fed the above described (A3) and outputs the above described 3rd output Q3 (Q3), and a 3rd output control circuit, the above described (A3) is connected to the above described (DQ3), the above described 3rd output control circuit has two inputs; the above described 3rd output Q3 (Q3) and the above described clock input (CK input), and an output (DO3) input to the above described (A3), and when the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described 3rd output Q3 (Q3) to the above described (DO3), and when the above described clock input (CK input) is at the 2nd logic level, holds the above described 3rd output Q3 (Q3) at high impedance, and the above described 3rd output Q3 (Q3) is connected to the above described test output (QT).
The semiconductor apparatus according to a fifth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the row latch circuit and column latch circuit are constructed of the latch circuit according to a fourth aspect.
The latch circuit according to a sixth aspect of the present invention is a latch circuit constructed of five inputs of clock input (CK input), enable signal input (/EN input), test control data input (NT), data input (D input) and test input (DT), and two outputs; an output Q and a test output (QT), 4th latch means and 5th latch means, characterized in that the above described 4th latch means is constructed of a 4th data input circuit and a 4th data holding circuit, the above described 4th data input circuit is fed the above described clock input (CK input), the above described enable signal input (/EN input) and the above described test control data input (NT) and the above described data input (D input) and outputs (DQ4) and when the above described test control data input (NT) is non-active (xe2x80x9cHxe2x80x9d), the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described data input (D input) to the above described (DQ4) and when the above described test control data input (NT) is active (xe2x80x9cHxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described (DT) to the above described (DQ4), and when the above described test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d) and the above described enable signal input (/EN input) is nonactive (xe2x80x9cHxe2x80x9d) or the above described clock input (CK input) is at the 2nd logic level, holds (DQ4) at high impedance, the above described 4th data holding circuit is constructed of an inverter that is fed (A4) and outputs the above described output Q and a 4th output control circuit, the above described (A4) is connected to the above described (DQ4), the above described 4th output control circuit has four inputs of the above described output Q (Q output), the above described clock input (CK input) and the above described enable signal input (/EN input) and the above described test control data input (NT), and an output (DO4) input to the above described (A4) and when the above described test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d) and the above described enable signal input (/EN input) is non-active (xe2x80x9cHxe2x80x9d) or the above described clock input (CK input) is at the 2nd logic level, outputs the inverted level of the above described output Q (Q output) to the above described (DO4) and when the above described test control data input (NT) is active (xe2x80x9cAHxe2x80x9d) or the above described enable signal input (/EN input) is active (xe2x80x9cLxe2x80x9d) and the above described clock input (CK input) is at the 1st logic level, holds the above described (DO4) at high impedance, the above described 5th latch means is constructed of a 5th data input circuit and the 3rd data holding circuit according to a fourth aspect, the above described 5th data input circuit has two inputs; a 5th data input (D5) and a 5th clock input (CK5), and an output (DQ5), and when the above described 5th clock input (CK5) is at the 2nd logic level, outputs the inverted level of the above described (D5) to the above described (DQ5) and when the above described 5th clock input (CK5) is at the 2nd logic level, holds the above described (DQS) at high impedance, the above described (DQ5) is connected to the above described (A3) of the above described 3rd data holding circuit, and the above described 5th data input (D5) is connected to the above described output Q, the above described 5th clock input (CK5) is connected to the above described clock input (CK input), and the above described (DQ5) is connected to the above described test output (QT).
The latch circuit according to a seventh aspect of the present invention is constructed of the two 2nd latch means according to a fourth aspect and the 3rd latch means according to a fourth aspect, characterized in that the 1st (D2) of the above described 2nd latch means is connected to the data input (D input) and the above described 2nd output Q2 (Q2 output) is connected to the above described output Q (Q output) and the above described (C3) of the above described 3rd latch means and the above described 2nd (D2) of the 2nd latch means is connected to the above described test input (DT) and the above described 2nd output Q2 (Q2) is connected to the above described (B3) of the above described 3rd latch means and the above described 3rd output Q3 (Q3) of the above described 3rd latch means is connected to the above described (QT).
The latch circuit according to an eighth aspect of the present invention is constructed of 6th latch means and the 5th latch means according to a sixth aspect, characterized in that the above described 6th latch means is constructed of a 6th data input circuit and the 2nd data holding circuit according to a fourth aspect, the above described 6th data input circuit is fed the above described clock input (CK input), the above described test control data input (NT) and the above described data input (D input) and outputs (DQ6), and when the above described test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d) and when the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described data input (D input) to the above described (DQ6) and when the above described test control data input (NT) is active (xe2x80x9cHxe2x80x9d) and when the above described clock input (CK input) is at the 1st logic level, outputs the inverted level of the above described test input (DT) to the above described (DQ6), and when the above described clock input (CK input) is at the 2nd logic level, holds (DQ6) at high impedance, the above described (A2) of the above described 2nd data holding circuit is connected to the above described (DQ6), the above described 2nd output Q2 (Q2) is connected to the above described output Q (Q output) and the 5th data input (D5 input) of the above described 5th latch means is connected to the above described output Q (Q output).
The latch circuit according to a ninth aspect of the present invention is characterized in that in the latch circuit according to a fourth aspect, the test output (QT) is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The latch circuit according to a tenth aspect of the present invention is characterized in that in the latch circuit according to a sixth aspect, the test output (QT) is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The latch circuit according to an eleventh aspect of the present invention is characterized in that in the latch circuit according to a seventh aspect, the test output (QT) is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The latch circuit according to a twelfth aspect of the present invention is characterized in that in the latch circuit according to an eighth aspect, the test output (QT) is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The semiconductor apparatus according to a thirteenth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit and the pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit are constructed of the latch circuit according to a sixth aspect.
The semiconductor apparatus according to a fourteenth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit and the pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit are constructed of the latch circuit according to ninth aspect.
The semiconductor apparatus according to a fifteenth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit and the pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit are constructed of the latch circuit according to a tenth aspect.
The semiconductor apparatus according to a sixteenth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the (DT input) of the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit or the pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The semiconductor apparatus according to a seventeenth aspect of the present invention is characterized in that in the semiconductor apparatus according to a first aspect, the test input (DT input) of the above described row latch circuit and the above described column latch circuit which is not connected to the test output (QT) of the kth (k: integer 1xe2x89xa6kxe2x89xa6m) row latch circuit or the pth (p: integer 1xe2x89xa6pxe2x89xa6n) column latch circuit is fixed to xe2x80x9cLxe2x80x9d or xe2x80x9cHxe2x80x9d when the test control data input (NT) is non-active (xe2x80x9cLxe2x80x9d).
The DRAM according to an eighteenth aspect of the present invention is characterized by comprising a plurality of memory cells, a plurality of bits line pairs connected to their respective sense amplifiers, an internal row selection control signal generation circuit that generates an internal row selection control signal synchronized with a clock input based on a row selection control signal input, a row address latch enable signal generation circuit that generates a row address latch enable signal, which is activated when the above described internal row selection control signal is non-active and inactivated when the above described internal row selection control signal is activated, a row address latch circuit that directly outputs a row address supplied from the outside when the above described row address latch enable signal is active and holds the row address internally when the above described row address latch enable signal is non-active, a row address decoder that receives the output of the above described row address latch circuit and operates even if the above described internal row selection control signal is non-active, and a sense amplifier activation signal generation circuit that generates a sense amplifier activation signal that activates the above described sense amplifier in response to the above described internal row selection control signal.
The DRAM according to a nineteenth aspect of the present invention is characterized in that in the DRAM according to an eighteenth aspect, the above described row address latch enable signal generation circuit holds the non-active state of the above described row address latch enable signal until the above described sense amplifier activation signal is inactivated.
The DRAM according to a twentieth aspect of the present invention is characterized in that in the DRAM according to an eighteenth aspect, the above described row address latch circuit operates in synchronization with the above described clock input and directly outputs the row address supplied from the outside only when the above described address latch enable signal is active and the above described clock input is at a predetermined logic level.
The DRAM according to a twenty-first aspect of the present invention comprises q bit lines, /bit lines and r main bit lines, /main bit lines to which a plurality of memory cells and sense amplifiers are connected, a 1st transistor, to the gate connecting the above described bit lines and main bit lines of which a connection control signal is input, a 2nd transistor, to the gate connecting the above described /bit lines and /main bit lines of which a connection control signal is input, a main amplifier that amplifies a potential difference between the above described main bit lines and /main bit lines, a latch circuit to latch the output of the above described main amplifier, and a timing generation circuit that generates a latch signal of the above described latch circuit, the above described connection control signal and /2nd latch enable signal of the above described column address latch circuit, a certain time after the clock edge of the clock cycle for carrying out a read operation of the above described memory cell, characterized in that the above described /2nd latch enable signal is driven xe2x80x9cLxe2x80x9d when the above described latch circuit completes the input of the output of the above described main amplifier and at timing at which the level of the above described latch signal becomes the level for holding data or at timing at which the above described connection control signal changes from the level for turning ON the above described 1st transistor and 2nd transistor to the level for turning OFF the above described 1st transistor and 2nd transistor, whichever is later, and is driven xe2x80x9cHxe2x80x9d in synchronization with the clock edge of the clock cycle for carrying out the next read or write operation. The above described column address latch circuit is characterized by directly outputting the input column address when the /2nd latch enable signal is xe2x80x9cLxe2x80x9d and the above described clock is at the 1st logic level and holds the output signal without inputting the above described column address when the /2nd latch enable signal is xe2x80x9cHxe2x80x9d or the above described clock is at the 2nd logic level.
The DRAM according to a twenty-second aspect of the present invention comprises q bit lines and /bit lines to which a plurality of memory cells and sense amplifiers are connected, r main bit lines and /main bit lines to which a write buffer outputs write data and /write data during an operation of writing to the above described memory cell, a 1st transistor, to the gate connecting the above described bit lines and main bit lines of which a connection control signal is input, a 2nd transistor, to the gate connecting the above described /bit lines and /main bit lines of which a connection control signal is input, a column address latch circuit and a timing generation circuit that detects the above described clock edge by receiving a clock as input and generates the above described connection control signal and the /2nd latch enable signal of the above described column address latch circuit, characterized in that the /2nd latch enable signal is driven xe2x80x9cLxe2x80x9d when the above described connection control signal changes from the level for turning ON the above described 1st transistor and 2nd transistor to the level for turning OFF the above described 1st transistor and 2nd transistor in the clock cycle of performing an operation of writing to the above described memory cell, and is driven xe2x80x9cHxe2x80x9d in synchronization with the clock edge of the clock cycle for carrying out the next read or write operation and the above described column address latch circuit directly outputs the column address input when the above described /2nd latch enable signal is xe2x80x9cLxe2x80x9d and the above described clock is at the 1st logic level and when the above described /2nd latch enable signal is nonactive (xe2x80x9cHxe2x80x9d) or when the above described clock is at the 2nd logic level, holds the output signal without inputting the above described column address.
The semiconductor apparatus according to a twenty-third aspect of the present invention is characterized in that in the semiconductor apparatus according to any one of a first, thirteenth, fourteenth, fifteenth, sixteenth and seventeenth aspect, the 1st /latch enable signal is a signal that is driven xe2x80x9cLxe2x80x9d when the above described sense amplifier activation signal according to an eighteenth aspect is at the level of inactivating the above described sense amplifier and the above described internal row selection control signal is at xe2x80x9cLxe2x80x9d and the 2nd /latch enable signal is driven xe2x80x9cLxe2x80x9d at the timing according to a sixteenth aspect in the clock cycle of read operation and is driven xe2x80x9cLxe2x80x9d at the timing according to a seventeenth aspect in the clock cycle of the write operation and is driven xe2x80x9cHxe2x80x9d in synchronization with the clock edge of the clock cycle that performs a read or write operation.